Llus Ribas
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
7
Venues
5
Active years
1994–2005
Best venue rank
A*
Where they publish
Papers
7 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2005 | FDL | Hardware Synthesis of Parallel Machines from SystemC. | Antoni Portero, Llus Ribas, Jordi Carrabina |
| 2003 | FDL | On Hardware Description in ECL. | Llus Ribas, Joaqun Saiz |
| 1999 | DATE | Digital MOS Circuit Partitioning with Symbolic Modeling. | Llus Ribas, Jordi Carrabina |
| 1998 | DATE | On the Reuse of Symbolic Simulation Results for Incremental Equivalence Verification of Switch-Level Circuits. | Llus Ribas, Jordi Carrabina |
| 1995 | DAC | Analysis of Switch-Level Faults by Symbolic Simulation. | Llus Ribas, Jordi Carrabina |
| 1995 | ISCAS | Symbolic Analysis for Fault Detection in Switch-Level Circuits. | Llus Ribas, Jordi Carrabina |
| 1994 | ICCD | Short Destabilizing Paths in Timing Verification. | Rafael Peset Llopis, Llus Ribas, Jordi Carrabina |