| 2018 | ISCAS | Lightweight Hardware Architecture for Probabilistic Gradient Descent Bit Flipping on QC-LDPC Codes. | Khoa Le, Fakhreddine Ghaffari, Lounis Kessal, David Declercq, Valentin Savin, Oana Boncalo |
| 2017 | PIMRC | Density evolution thresholds for noise-against-noise min-sum decoders. | Franklin Cochachin, David Declercq, Emmanuel Boutillon, Lounis Kessal |
| 2008 | ESANN | Neural network hardware architecture for pattern recognition in the HESS2 project. | Narayanan Ramanan, Sonia Khatchadourian, Jean-Christophe Prvotet, Lounis Kessal |
| 2004 | ICIP | Design flexibility using fpga dynamical reconfiguration. | Nicolas Abel, Lounis Kessal, Didier Demigny |
| 2000 | ICIP | Reconfigurable Hardware for Real Time Image Processing. | Lounis Kessal, Didier Demigny, N. Boudouani, R. Bourguiba |
| 1997 | ICIP | Efficient ASIC and FPGA Implementations of IIR Filters for Real Time Edge Detection. | F. G. Lorca, Lounis Kessal, Didier Demigny |
| 1995 | ICIP | Evaluation of edge detectors performances with a discrete expression of Canny's criteria. | Didier Demigny, F. G. Lorca, Lounis Kessal |