Luis Gabriel Murillo
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
10
Venues
6
Active years
2008–2016
Best venue rank
A*
Where they publish
Papers
10 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2016 | DAC | Automatic parallelization and accelerator offloading for embedded applications on heterogeneous MPSoCs. | Miguel Angel Aguilar, Rainer Leupers, Gerd Ascheid, Luis Gabriel Murillo |
| 2015 | ASPDAC | SWAT: Assertion-based debugging of concurrency issues at system level. | Luis Gabriel Murillo, Robert Lajos Bcs, Daniel Hincapie, Rainer Leupers, Gerd Ascheid |
| 2015 | FDL | Virtual hardware-in-the-loop co-simulation for multi-domain automotive systems via the functional mock-up interface. | Robert Lajos Bcs, Luis Gabriel Murillo, Ekaterina Korotcenko, Gaurav Dugge, Rainer Leupers, Gerd Ascheid, Andreas Ropers, Markus Wedler, Andreas Hoffmann |
| 2015 | SCOPES | Application-Specific Architecture Exploration Based on Processor-Agnostic Performance Estimation. | Juan Fernando Eusse, Luis Gabriel Murillo, Christopher McGirr, Rainer Leupers, Gerd Ascheid |
| 2014 | DATE | Automatic detection of concurrency bugs through event ordering constraints. | Luis Gabriel Murillo, Simon Wawroschek, Jernimo Castrilln, Rainer Leupers, Gerd Ascheid |
| 2014 | ISPA | EURETILE Design Flow: Dynamic and Fault Tolerant Mapping of Multiple Applications Onto Many-Tile Systems. | Lars Schor, Iuliana Bacivarov, Luis Gabriel Murillo, Pier Stanislao Paolucci, Frdric Rousseau, Ashraf El Antably, Robert Buecs, Nicolas Fournel, Rainer Leupers, Devendra Rai, Lothar Thiele, Laura Tosoratto, Piero Vicini, Jan Weinstock |
| 2012 | DAC | Synchronization for hybrid MPSoC full-system simulation. | Luis Gabriel Murillo, Juan Fernando Eusse, Jovana Jovic, Sergey Yakoushkin, Rainer Leupers, Gerd Ascheid |
| 2012 | DATE | Hybrid simulation for extensible processor cores. | Jovana Jovic, Sergey Yakoushkin, Luis Gabriel Murillo, Juan Fernando Eusse, Rainer Leupers, Gerd Ascheid |
| 2009 | FDL | Semi-automated Hw/Sw Co-design for embedded systems: from MARTE models to SystemC simulators. | Luis Gabriel Murillo, Marcello Mura, Mauro Prevostini |
| 2008 | FDL | Model-based Design Space Exploration for RTES with SysML and MARTE. | Marcello Mura, Luis Gabriel Murillo, Mauro Prevostini |