| 2021 | DDECS | EKV MOS Transistor Model For Ultra Low-Voltage Bulk-Driven IC Design. | Luks Nagy, Daniel Arbet, Martin Kovc, Miroslav Potocn, Michal Sovcik, Viera Stopjakov |
| 2020 | DDECS | Dynamic Properties Of Ultra Low-Voltage Rail-to-Rail Comparator Designed In 130 nm CMOS Technology. | Luks Nagy, Daniel Arbet, Martin Kovc, Miroslav Potocn, Michal Sovcik, Viera Stopjakov |
| 2019 | DDECS | Low Latency Hardware-Accelerated Dynamic Memory Manager for Hard Real-Time and Mixed-Criticality Systems. | Luks Kohtka, Luks Nagy, Viera Stopjakov |
| 2019 | DDECS | Investigation of Low-Voltage, Sub-threshold Charge Pump with Parasitics Aware Design Methodology. | Martin Kovc, Daniel Arbet, Viera Stopjakov, Michal Sovcik, Luks Nagy |
| 2019 | DDECS | Ultra Low-Voltage Rail-to-Rail Comparator Design in 130 nm CMOS Technology. | Luks Nagy, Daniel Arbet, Martin Kovc, Miroslav Potocn, Viera Stopjakov |
| 2018 | DDECS | Two-Stage Bulk-Driven Variable Gain Amplifier for Low-Voltage Applications. | Daniel Arbet, Martin Kovc, Luks Nagy, Viera Stopjakov, Michal Sovcik |
| 2018 | DDECS | Design and Performance Analysis of Ultra-Low Voltage Rail-to-Rail Comparator in 130 nm CMOS Technology. | Luks Nagy, Daniel Arbet, Martin Kovc, Miroslav Potocn, Viera Stopjakov |
| 2018 | DSD | A Novel Hardware-Accelerated Priority Queue for Real-Time Systems. | Luks Kohtka, Luks Nagy, Viera Stopjakov |
| 2016 | DDECS | Low-voltage bulk-driven variable gain amplifier in 130 nm CMOS technology. | Daniel Arbet, Martin Kovc, Luks Nagy, Viera Stopjakov, Juraj Brenkus |
| 2016 | DDECS | Impedance calculation based method for AC fault analysis of mixed-signal circuits. | Juraj Brenkus, Viera Stopjakov, Luks Nagy, Daniel Arbet |
| 2015 | DDECS | Design of In AlN/GaN Heterostructure-Based Logic Cells. | Luks Nagy, Viera Stopjakov, Alexander Satka |
| 2014 | ECAI | Novel architecture of a digital neuron for FFNN employing special multiplication. | Roman Zlusk, Daniela Durackov, Viera Stopjakov, Luks Nagy, Vladimr Sedlk |
| 2012 | DDECS | Current sensing completion detection in dual-rail asynchronous systems. | Luks Nagy, Viera Stopjakov |
| 2011 | DDECS | Current sensing methodology for completion detection in self-timed systems. | Luks Nagy, Viera Stopjakov |
| 2010 | DDECS | Current Sensing Completion Detection in deep sub-micron technologies. | Luks Nagy, Viera Stopjakov |