M. Bhuvanesh
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
1
Venues
1
Active years
2025–2025
Best venue rank
C
Where they publish
Papers
1 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2025 | ISCAS | A 2.9mW Inverter-based Quadrature Phase Clock Generator with ± 0.29° Phase Error. | Mayank Kumar Singh, M. Bhuvanesh, Rajasekhar Nagulapalli, Devarshi Mrinal Das, Mahendra Sakare |