M. Hanawa
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
2
Venues
1
Active years
1988–1991
Best venue rank
C
Where they publish
Papers
2 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 1991 | ICCD | On-Chip Multiple Superscalar Processors with Secondary Cache Memories. | M. Hanawa, Tadahiko Nishimukai, O. Nishii, Masato Suzuki, Kazuo Yano, Mitsuru Hiraki, Shoji Shukuri, Takashi Nishida |
| 1988 | ICCD | Cache-based pipeline architecture in the Hitachi H32/200 32-bit microprocessor. | Tadahiko Nishimukai, Hideo Inayoshi, Kikuko Takagi, Kazuhiko Iwasaki, Ikuya Kawasaki, M. Hanawa, Takeshi Okada |