| 2015 | VTC | Frequency Domain Aware Power Analysis Attack against Random Clock LSI for Secure Automotive Embedded Systems. | Masaya Yoshikawa, Yusuke Nozaki, Toshiya Asai, Kensaku Asahi |
| 2015 | SNPD | Power analysis for clock fluctuation LSI. | Yusuke Nozaki, Toshiya Asai, Kensaku Asahi, Masaya Yoshikawa |
| 2014 | ICSEng | Vulnerability evaluation of multiplexing PUF for SVM attacks. | S. Kiryu, Kensaku Asahi, Masaya Yoshikawa |
| 2014 | SNPD | Error value driven fault analysis attack. | Masaya Yoshikawa, Hikaru Goto, Kensaku Asahi |
| 2012 | IRI | Multiplexing aware arbiter physical unclonable function. | Masaya Yoshikawa, Akira Naruse |
| 2011 | IRI | Multi-rounds masking method against DPA attacks. | Masaya Yoshikawa, M. Sugiyama |
| 2011 | ICSEng | Efficient Random Number for the Masking Method against DPA Attacks. | Masaya Yoshikawa, Y. Kojima |
| 2010 | CAINE | Placement Tool Dedicated for a Via-programmable Logic Device VPEX. | Masaya Yoshikawa, Yuichi Kokusyo, Takeshi Fujino |
| 2010 | IRI | Hybrid Ant Colony Optimization for intensification and diversification. | Masaya Yoshikawa, Shimohigashi Yoshiaki |
| 2009 | IRI | Adaptive Immune Algorithm Considering Intensification and Diversification. | Masaya Yoshikawa, Akira Naruse, Shinsuke Souboku |
| 2009 | ISCAS | An Efficient Hardware Accelerator for Power Grid Simulation. | Taiki Hashizume, Hisako Sugano, Shinichi Nishizawa, Masaya Yoshikawa, Masahiro Fukui |
| 2008 | IRI | Route selection algorithm based on integer operation Ant Colony Optimization. | Masaya Yoshikawa, Hidekazu Terai |
| 2007 | IRI | Architecture for high-speed Ant Colony Optimization. | Masaya Yoshikawa, Hidekazu Terai |
| 2006 | CAINE | Co-evolutionary robotics using two kinds of neural networks. | Masaya Yoshikawa, Hidekazu Terai |
| 2006 | CATA | Immune Algorithm Processor. | Masaya Yoshikawa, Masahiro Fukui, Hidekazu Terai |
| 2006 | SERA | Apriori, Association Rules, Data Mining, Frequent Itemsets Mining (FIM), Parallel Computing. | Masaya Yoshikawa, Hidekazu Terai |
| 2005 | CEC | Performance driven placement technique based on collaboration of software and hardware. | Masaya Yoshikawa, Hidekazu Terai |
| 2005 | ISDA | A Hierarchical Parallel Placement Technique based on Genetic Algorithm. | Masaya Yoshikawa, Hidekazu Terai |
| 2005 | SERA | Asynchronous Parallel Genetic Algorithm for Congestion-Driven Placement Technique. | Masaya Yoshikawa, Hidekazu Terai |
| 2004 | ISCAS | VLSI processor architecture for real-time GA processing and PE-VLSI design. | Tetsuya Imai, Masaya Yoshikawa, Hidekazu Terai, Hironori Yamauchi |
| 2002 | ICASSP | Scalable GA processor architecture and its implementation of processor-element. | Tetsuya Imai, Masaya Yoshikawa, Hidekazu Terai, Hironori Yamauchi |