Mateja Putic
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
5
Venues
3
Active years
2008–2018
Best venue rank
A*
Where they publish
Papers
5 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2018 | DAC | Dyhard-DNN: even more DNN acceleration with dynamic hardware reconfiguration. | Mateja Putic, Swagath Venkataramani, Schuyler Eldridge, Alper Buyuktosunoglu, Pradip Bose, Mircea Stan |
| 2014 | DAC | Low Power GPGPU Computation with Imprecise Hardware. | Hang Zhang, Mateja Putic, John C. Lach |
| 2013 | ISCAS | Balancing Adder for error tolerant applications. | Matthew Weber, Mateja Putic, Hang Zhang, John C. Lach, Jiawei Huang |
| 2009 | ICCD | Panoptic DVS: A fine-grained dynamic voltage scaling framework for energy scalable CMOS design. | Mateja Putic, Liang Di, Benton H. Calhoun, John C. Lach |
| 2008 | ICCD | Power switch characterization for fine-grained dynamic voltage scaling. | Liang Di, Mateja Putic, John C. Lach, Benton H. Calhoun |