| 2025 | DATE | AraXL: A Physically Scalable, Ultra-Wide RISC-V Vector Processor Design for Fast and Efficient Computation on Long Vectors. | Navaneeth Kunhi Purayil, Matteo Perotti, Tim Fischer, Luca Benini |
| 2025 | ICCD | TROOP: At-the-Roofline Performance for Vector Processors on Low Operational Intensity Workloads. | Navaneeth Kunhi Purayil, Diyou Shen, Matteo Perotti, Luca Benini |
| 2024 | DATE | MX: Enhancing RISC-V's Vector ISA for Ultra-Low Overhead, Energy-Efficient Matrix Multiplication. | Matteo Perotti, Yichao Zhang, Matheus A. Cavalcante, Enis Mustafa, Luca Benini |
| 2024 | DATE | Near-Memory Parallel Indexing and Coalescing: Enabling Highly Efficient Indirect Access for SpMV. | Chi Zhang, Paul Scheffler, Thomas Benz, Matteo Perotti, Luca Benini |
| 2023 | DATE | AXI-Pack: Near-Memory Bus Packing for Bandwidth-Efficient Irregular Workloads. | Chi Zhang, Paul Scheffler, Thomas Benz, Matteo Perotti, Luca Benini |
| 2023 | ISCAS | Quark: An Integer RISC-V Vector Processor for Sub-Byte Quantized DNN Inference. | MohammadHossein AskariHemmat, Tho Dupuis, Yoan Fournier, Nizar El Zarif, Matheus A. Cavalcante, Matteo Perotti, Frank K. Grkaynak, Luca Benini, Franois Leduc-Primeau, Yvon Savaria, Jean-Pierre David |
| 2022 | ICCAD | Spatz: A Compact Vector Processing Unit for High-Performance and Energy-Efficient Shared-L1 Clusters. | Matheus A. Cavalcante, Domenic Wthrich, Matteo Perotti, Samuel Riedel, Luca Benini |
| 2021 | ISCAS | Tiny-FPU: Low-Cost Floating-Point Support for Small RISC-V MCU Cores. | Luca Bertaccini, Matteo Perotti, Stefan Mach, Pasquale Davide Schiavone, Florian Zaruba, Luca Benini |