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Mengjie Mao

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

15

Venues

7

Active years

2010–2016

Best venue rank

A*

Where they publish

Papers

15 indexed papers, newest first.

YearVenueTitleAuthors
2016DACTEMP: thread batch enabled memory partitioning for GPU.Mengjie Mao, Wujie Wen, Xiaoxiao Liu, Jingtong Hu, Danghui Wang, Yiran Chen, Hai Li
2016DATESliding Basket: An adaptive ECC scheme for runtime write failure suppression of STT-RAM cache.Xue Wang, Mengjie Mao, Enes Eken, Wujie Wen, Hai Li, Yiran Chen
2016DATEA holistic tri-region MLC STT-RAM design with combined performance, energy, and reliability optimizations.Wujie Wen, Mengjie Mao, Hai Li, Yiran Chen, Yukui Pei, Ning Ge
2016ISCASHeterogeneous systems with reconfigurable neuromorphic computing accelerators.Sicheng Li, Xiaoxiao Liu, Mengjie Mao, Hai (Helen) Li, Yiran Chen, Boxun Li, Yu Wang
2015ASPDACAn efficient STT-RAM-based register file in GPU architectures.Xiaoxiao Liu, Mengjie Mao, Xiuyuan Bi, Hai Li, Yiran Chen
2015DACRENO: a high-efficient reconfigurable neuromorphic computing accelerator design.Xiaoxiao Liu, Mengjie Mao, Beiye Liu, Hai Li, Yiran Chen, Boxun Li, Yu Wang, Hao Jiang, Mark Barnell, Qing Wu, Jianhua Joshua Yang
2015DACVWS: a versatile warp scheduler for exploring diverse cache localities of GPGPU applications.Mengjie Mao, Jingtong Hu, Yiran Chen, Hai Li
2015ISCASThe applications of memristor devices in next-generation cortical processor designs.Hai Li, Beiye Liu, Xiaoxiao Liu, Mengjie Mao, Yiran Chen, Qing Wu, Qinru Qiu
2014ASPDACPrefetching techniques for STT-RAM based last-level cache in CMP systems.Mengjie Mao, Guangyu Sun, Yong Li, Alex K. Jones, Yiran Chen
2014DACExploration of GPGPU Register File Architecture Using Domain-wall-shift-write based Racetrack Memory.Mengjie Mao, Wujie Wen, Yaojun Zhang, Yiran Chen, Hai (Helen) Li
2014DACState-Restrict MLC STT-RAM Designs for High-Reliable High-Performance Memory System.Wujie Wen, Yaojun Zhang, Mengjie Mao, Yiran Chen
2013ICCADUnleashing the potential of MLC STT-RAM caches.Xiuyuan Bi, Mengjie Mao, Danghui Wang, Hai Li
2013ICCADCD-ECC: content-dependent error correction codes for combating asymmetric nonvolatile memory operation errors.Wujie Wen, Mengjie Mao, Xiaochun Zhu, Seung-Hyuk Kang, Danghui Wang, Yiran Chen
2012ICSDistributed replay protocol for distributed uniprocessors.Mengjie Mao, Hong An, Bobin Deng, Tao Sun, Xuechao Wei, Wei Zhou, Wenting Han
2010PDCATFACRA: Flexible-Core Architecture Chip Resource Abstractor.Tao Sun, Hong An, Yongqing Ren, Mengjie Mao, Yang Liu, Mu Xu, Qi Li