| 2005 | DAC | Spatially distributed 3D circuit models. | Michael W. Beattie, Hui Zheng, Anirudh Devgan, Byron Krauter |
| 2002 | DAC | On the efficacy of simplified 2D on-chip inductance models. | Tao Lin, Michael W. Beattie, Lawrence T. Pileggi |
| 2002 | DATE | On-Chip Inductance Models: 3D or Not 3D? | Tao Lin, Michael W. Beattie, Lawrence T. Pileggi |
| 2002 | DATE | Window-Based Susceptance Models for Large-Scale RLC Circuit Analyses. | Hui Zheng, Lawrence T. Pileggi, Michael W. Beattie, Byron Krauter |
| 2001 | DAC | Inductance 101: Modeling and Extraction. | Michael W. Beattie, Lawrence T. Pileggi |
| 2001 | DAC | Modeling Magnetic Coupling for On-Chip Interconnect. | Michael W. Beattie, Lawrence T. Pileggi |
| 2001 | DATE | Efficient inductance extraction via windowing. | Michael W. Beattie, Lawrence T. Pileggi |
| 2000 | ICCAD | Hierarchical Interconnect Circuit Models. | Michael W. Beattie, Satrajit Gupta, Lawrence T. Pileggi |
| 1999 | DAC | IC Analyses Including Extracted Inductance Models. | Michael W. Beattie, Lawrence T. Pileggi |
| 1999 | ICCAD | Electromagnetic parasitic extraction via a multipole method with hierarchical refinement. | Michael W. Beattie, Lawrence T. Pileggi |
| 1997 | DAC | Bounds for BEM Capacitance Extraction. | Michael W. Beattie, Lawrence T. Pileggi |