Minoru Yamada
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
2
Venues
2
Active years
1981–1990
Best venue rank
A*
Where they publish
Papers
2 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 1990 | IJCNN | Design, fabrication and evaluation of a 5-inch wafer scale neural network LSI composed on 576 digital neurons. | Moritoshi Yasunaga, Noboru Masuda, Masayoshi Yagyu, Mitsuo Asai, Minoru Yamada, Akira Masaki |
| 1981 | DAC | A critical path delay check system. | Ryotaro Kamikawai, Minoru Yamada, Tsuneyo Chiba, Kenichi Furumaya, Yoji Tsuchiya |