Skip to content

Mitesh R. Meswani

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

7

Venues

4

Active years

2011–2017

Best venue rank

A*

Where they publish

Papers

7 indexed papers, newest first.

YearVenueTitleAuthors
2017HPCAMemPod: A Clustered Architecture for Efficient and Scalable Migration in Flat Address Space Multi-level Memories.Andreas Prodromou, Mitesh R. Meswani, Nuwan Jayasena, Gabriel H. Loh, Dean M. Tullsen
2017HPCASILC-FM: Subblocked InterLeaved Cache-Like Flat Memory Organization.Jee Ho Ryoo, Mitesh R. Meswani, Andreas Prodromou, Lizy K. John
2017HPCADesign and Analysis of an APU for Exascale Computing.Thiruvengadam Vijayaraghavan, Yasuko Eckert, Gabriel H. Loh, Michael J. Schulte, Mike Ignatowski, Bradford M. Beckmann, William C. Brantley, Joseph L. Greathouse, Wei Huang, Arun Karunanithi, Onur Kayiran, Mitesh R. Meswani, Indrani Paul, Matthew Poremba, Steven Raasch, Steven K. Reinhardt, Greg Sadowski, Vilas Sridharan
2015HPCAHeterogeneous memory architectures: A HW/SW approach for mixing die-stacked and off-package memories.Mitesh R. Meswani, Sergey Blagodurov, David Roberts, John Slice, Mike Ignatowski, Gabriel H. Loh
2014SCToward efficient programmer-managed two-level memory hierarchies in exascale computers.Mitesh R. Meswani, Gabriel H. Loh, Sergey Blagodurov, David Roberts, John Slice, Mike Ignatowski
2013PLDIA new perspective on processing-in-memory architecture design.Dong Ping Zhang, Nuwan Jayasena, Alexander Lyashevsky, Joseph L. Greathouse, Mitesh R. Meswani, Mark Nutter, Mike Ignatowski
2011EuroParReducing Energy Usage with Memory and Computation-Aware Dynamic Frequency Scaling.Michael Laurenzano, Mitesh R. Meswani, Laura Carrington, Allan Snavely, Mustafa M. Tikir, Stephen Poole