| 2015 | ASPDAC | H.265/HEVC encoder for UHDTV. | Mitsuo Ikeda |
| 2013 | ICIP | Residue role assignment based transform partition predetermination on HEVC. | Jia Su, Koyo Nitta, Mitsuo Ikeda, Atsushi Shimizu |
| 2008 | ISCAS | Multi-reference and multi-block-size motion estimation with flexible mode selection for professional 4: 2: 2 H.264/AVC encoder LSI. | Takayuki Onishi, Takashi Sano, Koyo Nitta, Mitsuo Ikeda, Jiro Naganuma |
| 2004 | ISCAS | A distributed TS-MUX architecture for multi-chip extension beyond the HDTV level. | Takayuki Onishi, Mitsuo Ikeda, Jiro Naganuma, Makoto Endo, Yoshiyuki Yashima |
| 2003 | DATE | Single-Chip MPEG-2 422P@HL CODEC LSI with Multi-Chip Configuration for Large Scale Processing beyond HDTV Level. | Hiroe Iwasaki, Jiro Naganuma, Koyo Nitta, Ken Nakamura, Takeshi Yoshitome, Mitsuo Ogura, Yasuyuki Nakajima, Yutaka Tashiro, Takayuki Onishi, Mitsuo Ikeda, Makoto Endo |
| 1999 | DATE | An MPEG-2 Video Encoder LSI with Scalability for HDTV based on Three-layer Cooperative Architecture. | Mitsuo Ikeda, Toshio Kondo, Koyo Nitta, Kazuhito Suguri, Takeshi Yoshitome, Toshihiro Minami, Jiro Naganuma, Takeshi Ogura |
| 1996 | DATE | A Hardware/Software Concurrent Design for a Real-Time SP@ML MPEG2 Video-Encoder Chip Set. | Mitsuo Ikeda, Tsuneo Okubo, Tetsuya Abe, Yoshinori Ito, Yutaka Tashiro, Ryota Kasai |