| 2018 | ISORC | A Self-Reconfiguring Cache Architecture to Improve Control Quality in Cyber-Physical Systems. | Mohammad Shihabul Haque, Sriram Vasudevan, Alamuri Sriram Nihar, Arvind Easwaran, Akash Kumar, Y. C. Tay |
| 2015 | ASPDAC | Accelerating non-volatile/hybrid processor cache design space exploration for application specific embedded systems. | Mohammad Shihabul Haque, Ang Li, Akash Kumar, Qingsong Wei |
| 2013 | ASPDAC | TRISHUL: A single-pass optimal two-level inclusive data cache hierarchy selection process for real-time MPSoCs. | Mohammad Shihabul Haque, Akash Kumar, Yajun Ha, Qiang Wu, Shaobo Luo |
| 2011 | ICCAD | CIPARSim: Cache intersection property assisted rapid single-pass FIFO cache simulation technique. | Mohammad Shihabul Haque, Jorgen Peddersen, Sri Parameswaran |
| 2010 | DAC | SCUD: a fast single-pass L1 cache simulation approach for embedded processors with round-robin replacement policy. | Mohammad Shihabul Haque, Jorgen Peddersen, Andhi Janapsatya, Sri Parameswaran |
| 2010 | DATE | DEW: A fast level 1 cache simulation approach for embedded processors with FIFO replacement policy. | Mohammad Shihabul Haque, Jorgen Peddersen, Andhi Janapsatya, Sri Parameswaran |
| 2010 | DATE | Rapid runtime estimation methods for pipelined MPSoCs. | Haris Javaid, Andhi Janapsatya, Mohammad Shihabul Haque, Sri Parameswaran |