| 2025 | ISCAS | Bit-Width-Aware Design Environment for Few-Shot Learning on Edge AI Hardware. | R. Kanda, Hugo Le Blevec, Naoya Onizawa, Mathieu Lonardon, Vincent Gripon, Takahiro Hanyu |
| 2021 | ISCAS | High Convergence Rates of CMOS Invertible Logic Circuits Based on Many-Body Hamiltonians. | Naoya Onizawa, Takahiro Hanyu |
| 2019 | ACSSC | A Design Framework for Invertible Logic. | Naoya Onizawa, Kaito Nishino, Sean C. Smithson, Brett H. Meyer, Warren J. Gross, Hitoshi Yamagata, Hiroyuki Fujita, Takahiro Hanyu |
| 2018 | ISCAS | High-Precision Stochastic State-Space Digital Filters Based on Minimum Roundoff Noise Structure. | Shunsuke Koshita, Naoya Onizawa, Masahide Abe, Takahiro Hanyu, Masayuki Kawamata |
| 2017 | DATE | Three-terminal MTJ-based nonvolatile logic circuits with self-terminated writing mechanism for ultra-low-power VLSI processor. | Takahiro Hanyu, Daisuke Suzuki, Naoya Onizawa, Masanori Natsui |
| 2016 | ICASSP | Gammatone filter based on stochastic computation. | Naoya Onizawa, Shunsuke Koshita, Shuichi Sakamoto, Masahide Abe, Masayuki Kawamata, Takahiro Hanyu |
| 2015 | DATE | Spintronics-based nonvolatile logic-in-memory architecture towards an ultra-low-power and highly reliable VLSI computing paradigm. | Takahiro Hanyu, Daisuke Suzuki, Naoya Onizawa, Shoun Matsunaga, Masanori Natsui, Akira Mochizuki |
| 2013 | DAC | Low-power area-efficient large-scale IP lookup engine based on binary-weighted clustered networks. | Naoya Onizawa, Warren J. Gross |
| 2013 | ICASSP | Reduced-complexity binary-weight-coded associative memories. | Hooman Jarollahi, Naoya Onizawa, Vincent Gripon, Warren J. Gross |
| 2012 | ISCAS | Architecture and implementation of an associative memory using sparse clustered networks. | Hooman Jarollahi, Naoya Onizawa, Vincent Gripon, Warren J. Gross |
| 2012 | PRDC | Multi-chip NoCs for Automotive Applications. | Tomohiro Yoneda, Masashi Imai, Naoya Onizawa, Atsushi Matsumoto, Takahiro Hanyu |
| 2011 | DATE | Interconnect-fault-resilient delay-insensitive asynchronous communication link based on current-flow monitoring. | Naoya Onizawa, Atsushi Matsumoto, Takahiro Hanyu |
| 2011 | ISCAS | Adjacent-State monitoring based fine-grained power-gating scheme for a low-power asynchronous pipelined system. | Takao Kawano, Naoya Onizawa, Atsushi Matsumoto, Takahiro Hanyu |
| 2010 | ISCAS | High-throughput protocol converter based on an independent encoding/decoding scheme for asynchronous Network-on-Chip. | Naoya Onizawa, Takahiro Hanyu |
| 2009 | ISCAS | High-performance Asynchronous Intra-chip Communication Link based on a Multiple-valued Current-mode Single-track Scheme. | Yo Ohtake, Naoya Onizawa, Takahiro Hanyu |