Naresh Maheshwari
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
4
Venues
4
Active years
1996–1998
Best venue rank
A*
Where they publish
Papers
4 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 1998 | DATE | Efficient Minarea Retiming of Large Level-Clocked Circuits. | Naresh Maheshwari, Sachin S. Sapatnekar |
| 1997 | DAC | An Improved Algorithm for Minimum-Area Retiming. | Naresh Maheshwari, Sachin S. Sapatnekar |
| 1997 | ICCAD | Minimum area retiming with equivalent initial states. | Naresh Maheshwari, Sachin S. Sapatnekar |
| 1996 | ICCD | A Practical Algorithm for Retiming Level-Clocked Circuits. | Naresh Maheshwari, Sachin S. Sapatnekar |