| 2010 | DATE | Efficient 3D high-frequency impedance extraction for general interconnects and inductors above a layered substrate. | Navin Srivastava, Roberto Suaya, Kaustav Banerjee |
| 2008 | DATE | High-Frequency Mutual Impedance Extraction of VLSI Interconnects In the Presence of a Multi-layer Conducting Substrate. | Navin Srivastava, Roberto Suaya, Kaustav Banerjee |
| 2006 | ASPDAC | Electrothermal engineering in the nanometer era: from devices and interconnects to circuits and systems. | Kaustav Banerjee, Sheng-Chih Lin, Navin Srivastava |
| 2006 | ASPLOS | Introspective 3D chips. | Shashidhar Mysore, Banit Agrawal, Navin Srivastava, Sheng-Chih Lin, Kaustav Banerjee, Timothy Sherwood |
| 2006 | DAC | Are carbon nanotubes the future of VLSI interconnections? | Kaustav Banerjee, Navin Srivastava |
| 2006 | DAC | A thermally-aware performance analysis of vertically integrated (3-D) processor-memory hierarchy. | Gian Luca Loi, Banit Agrawal, Navin Srivastava, Sheng-Chih Lin, Timothy Sherwood, Kaustav Banerjee |
| 2005 | ICCAD | Performance analysis of carbon nanotube interconnects for VLSI applications. | Navin Srivastava, Kaustav Banerjee |
| 2005 | ICCD | A Thermally-Aware Methodology for Design-Specific Optimization of Supply and Threshold Voltages in Nanometer Scale ICs. | Sheng-Chih Lin, Navin Srivastava, Kaustav Banerjee |