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Ne Kyaw Zwa Lwin

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

10

Venues

1

Active years

2015–2022

Best venue rank

C

Where they publish

Papers

10 indexed papers, newest first.

YearVenueTitleAuthors
2022ISCASNon-profiling based Correlation Optimization Deep Learning Analysis.Juncheng Chen, Jun-Sheng Ng, Nay Aung Kyaw, Ne Kyaw Zwa Lwin, Kwen-Siong Chong, Zhiping Lin, Joseph Sylvester Chang, Bah-Hwee Gwee
2022ISCASAn Asynchronous-Logic Masked Advanced Encryption Standard (AES) Accelerator and its Side-Channel Attack Evaluations.Jun-Sheng Ng, Juncheng Chen, Nay Aung Kyaw, Ne Kyaw Zwa Lwin, Kwen-Siong Chong, Joseph S. Chang, Bah-Hwee Gwee
2021ISCASNormalized Differential Power Analysis - for Ghost Peaks Mitigation.Juncheng Chen, Jun-Sheng Ng, Nay Aung Kyaw, Ne Kyaw Zwa Lwin, Weng-Geng Ho, Kwen-Siong Chong, Zhiping Lin, Joseph Sylvester Chang, Bah-Hwee Gwee
2020ISCASRadiation-Hardened-by-Design (RHBD) Digital Design Approaches: A Case Study on an 8051 Microcontroller.Kwen-Siong Chong, Ne Kyaw Zwa Lwin, Wei Shu, Joseph S. Chang
2020ISCASA DPA-Resistant Asynchronous-Logic NoC Router with Dual-Supply-Voltage-Scaling for Multicore Cryptographic Applications.Weng-Geng Ho, Ne Kyaw Zwa Lwin, Nay Aung Kyaw, Jun-Sheng Ng, Juncheng Chen, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang
2020ISCASA Highly Efficient Power Model for Correlation Power Analysis (CPA) of Pipelined Advanced Encryption Standard (AES).Jun-Sheng Ng, Juncheng Chen, Nay Aung Kyaw, Ne Kyaw Zwa Lwin, Weng-Geng Ho, Kwen-Siong Chong, Bah-Hwee Gwee
2019ISCASLow Gate-Count Ultra-Small Area Nano Advanced Encryption Standard (AES) Design.Aparna Shreedhar, Kwen-Siong Chong, Ne Kyaw Zwa Lwin, Nay Aung Kyaw, L. Nalangilli, Wei Shu, Joseph S. Chang, Bah-Hwee Gwee
2016ISCASTotal Ionizing Dose (TID) effects on finger transistors in a 65nm CMOS process.Jize Jiang, Wei Shu, Kwen-Siong Chong, Tong Lin, Ne Kyaw Zwa Lwin, Joseph Sylvester Chang, Jingyuan Liu
2016ISCASExperimental investigation into radiation-hardening-by-design (RHBD) flip-flop designs in a 65nm CMOS process.Tong Lin, Kwen-Siong Chong, Wei Shu, Ne Kyaw Zwa Lwin, Jize Jiang, Joseph S. Chang
2015ISCASHigh robustness energy- and area-efficient dynamic-voltage-scaling 4-phase 4-rail asynchronous-logic Network-on-Chip (ANoC).Weng-Geng Ho, Kwen-Siong Chong, Ne Kyaw Zwa Lwin, Bah-Hwee Gwee, Joseph S. Chang