Noboru Sakimura
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
3
Venues
1
Active years
2012–2014
Best venue rank
C
Where they publish
Papers
3 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2014 | ISCAS | A delay circuit with 4-terminal magnetic-random-access-memory device for power-efficient time- domain signal processing. | Ryusuke Nebashi, Noboru Sakimura, Hiroaki Honjo, Ayuka Morioka, Yukihide Tsuji, Kunihiko Ishihara, Keiichi Tokutome, Sadahiko Miura, Shunsuke Fukami, Keizo Kinoshita, Takahiro Hanyu, Tetsuo Endoh, Naoki Kasai, Hideo Ohno, Tadahiko Sugibayashi |
| 2013 | ISCAS | MTJ/MOS-hybrid logic-circuit design flow for nonvolatile logic-in-memory LSI. | Masanori Natsui, Takahiro Hanyu, Noboru Sakimura, Tadahiko Sugibayashi |
| 2012 | ISCAS | High-speed simulator including accurate MTJ models for spintronics integrated circuit design. | Noboru Sakimura, Ryusuke Nebashi, Yukihide Tsuji, Hiroaki Honjo, Tadahiko Sugibayashi, Hiroki Koike, Takashi Ohsawa, Shunsuke Fukami, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh |