Norito Kato
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
6
Venues
1
Active years
2003–2005
Best venue rank
National
Where they publish
Papers
6 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2005 | PDPTA | A New Model of Reconfigurable Cache for an SMT Processor and its FPGA Implementation. | Yoshiyasu Ogasawara, Norito Kato, Masanori Yamato, Mikiko Sato, Koichi Sasada, Kaname Uchikura, Mitaro Namiki, Hironori Nakajo |
| 2005 | PDPTA | Development of a Thread Scheduler for SMT Processor Architecture. | Kaname Uchikura, Koichi Sasada, Mikiko Sato, Masanori Yamato, Norito Kato, Hironori Nakajo, Mitaro Namiki |
| 2004 | PDPTA | Dynamic Allocation of Physical Register Banks for an SMT Processor. | Norito Kato, Masanori Yamato, Osamu Tujimoto, Mikiko Sato, Koichi Sasada, Kaname Uchikura, Mitaro Namiki, Hironori Nakajo |
| 2003 | PDPTA | Performance Evaluation of an On-Chip Multi-Threaded Processor with Cache Memory Managed by Logical Thread Number. | Hironori Nakajo, Masanori Yamato, Shoji Kawahara, Norito Kato, Koichi Sasada, Mikiko Sato, Mitaro Namiki |
| 2003 | PDPTA | Implementation and Evaluation of a Thread Library for Multithreaded Architecture. | Koichi Sasada, Mikiko Sato, Shoji Kawahara, Norito Kato, Masanori Yamato, Hironori Nakajo, Mitaro Namiki |
| 2003 | PDPTA | A Process and Thread Management of the Operating System "Future" for On Chip Multithreaded Architecture. | Mikiko Sato, Koichi Sasada, Shoji Kawahara, Norito Kato, Masanori Yamato, Hironori Nakajo, Mitaro Namiki |