Omid Azizi
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
8
Venues
6
Active years
2007–2014
Best venue rank
A*
Where they publish
Papers
8 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2014 | ASPLOS | SI-TM: reducing transactional memory abort rates through snapshot isolation. | Heiner Litz, David R. Cheriton, Amin Firoozshahian, Omid Azizi, John P. Stevenson |
| 2013 | HPCA | Hybrid latency tolerance for robust energy-efficiency on 1000-core data parallel processors. | Neal Clayton Crago, Omid Azizi, Steven S. Lumetta, Sanjay J. Patel |
| 2012 | ASPLOS | HICAMP: architectural support for efficient concurrency-safe shared structured data access. | David R. Cheriton, Amin Firoozshahian, Alex Solomatnikov, John P. Stevenson, Omid Azizi |
| 2010 | DATE | An integrated framework for joint design space exploration of microarchitecture and circuits. | Omid Azizi, Aqeel Mahesri, John P. Stevenson, Sanjay J. Patel, Mark Horowitz |
| 2010 | ISCA | Energy-performance tradeoffs in processor architecture and circuit design: a marginal cost analysis. | Omid Azizi, Aqeel Mahesri, Benjamin C. Lee, Sanjay J. Patel, Mark Horowitz |
| 2010 | ISCA | Understanding sources of inefficiency in general-purpose chips. | Rehan Hameed, Wajahat Qadeer, Megan Wachs, Omid Azizi, Alex Solomatnikov, Benjamin C. Lee, Stephen Richardson, Christos Kozyrakis, Mark Horowitz |
| 2008 | ISPASS | Processor Performance Modeling using Symbolic Simulation. | Omid Azizi, Jamison D. Collins, Dinesh Patil, Hong Wang, Mark Horowitz |
| 2007 | ARITH | Robust Energy-Efficient Adder Topologies. | Dinesh Patil, Omid Azizi, Mark Horowitz, Ron Ho, Rajesh Ananthraman |