Pai-Tse Chiang
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
2
Venues
1
Active years
2013–2013
Best venue rank
C
Where they publish
Papers
2 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2013 | ISCAS | A reconfigurable inverse transform architecture design for HEVC decoder. | Pai-Tse Chiang, Tian-Sheuan Chang |
| 2013 | ISCAS | Fast zero block detection and early CU termination for HEVC Video Coding. | Pai-Tse Chiang, Tian-Sheuan Chang |