Panu Sjvall
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
7
Venues
4
Active years
2018–2025
Best venue rank
C
Where they publish
Papers
7 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2025 | DSD | ShapeFuture - Technical Progress After Year 1. | Norbert Druml, Martin Gschwandtner, Mayeul Jeannin, Rainer Matischek, Edgars Lielamurs, Maksis Celitans, Kaspars Ozols, Nurullah Demiralay, Besir Tayfur, Ismail Sinan Gulbas, Nadir Kucuk, Isa Kiyat, Yahya Nasolo, Jens Uwe Brandt, Noah Christoph Ptz, Thomas Bartz-Beielstein, Jose Isola, Nikola Mandic, Francesca Flamigni, Alexander Kuehhas, Gianluca Brilli, Paolo Burgio, Giacomo Paolieri, Jorge Villagra, lvaro Flores Cueto, Jos Antonio Snchez, Jacopo Sini, Massimo Violante, Lorenzo Giraudi, Paolo Santero, Uwe Klbel, Moritz Schaffenroth, Panu Sjvall, Jarno Vanne, Morten Larsen, Nergis Gizem Yilmaz, Ziya Uygar Yengin, George Dimitrakopoulos |
| 2025 | VCIP | High-Level Synthesis FPGA Implementation of Fractional Motion Estimation for HEVC and VVC. | Jesse Smedberg, Panu Sjvall, Guillaume Gautier, Alexandre Mercat, Jarno Vanne |
| 2023 | ICIP | FPGA-Accelerated HEVC Encoder for Energy-Efficient Multi-Access Edge Computing. | Panu Sjvall, Alexandre Mercat, Jarno Vanne |
| 2021 | ISCAS | High-Level Synthesis Implementation of Transform-Exempted SATD Architectures for Low-Power Video Coding. | Tero Partanen, Ari Lemmetti, Panu Sjvall, Jarno Vanne |
| 2019 | VCIP | Visualization of Dynamic Resource Allocation for HEVC Encoding in FPGA-Accelerated SDN Cloud. | Panu Sjvall, Mikko Teuho, Arto Oinonen, Jarno Vanne, Timo D. Hmlinen |
| 2018 | ISCAS | FPGA-Powered 4K120p HEVC Intra Encoder. | Panu Sjvall, Vili Viitamki, Jarno Vanne, Timo D. Hmlinen, Ari Kulmala |
| 2018 | ISCAS | Live Demonstration: 4K100p HEVC Intra Encoder. | Vili Viitamki, Panu Sjvall, Jarno Vanne, Timo D. Hmlinen, Ari Kulmala |