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Paul Villarrubia

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

11

Venues

5

Active years

1989–2007

Best venue rank

A*

Where they publish

Papers

11 indexed papers, newest first.

YearVenueTitleAuthors
2007ASPDACFast Electrical Correction Using Resizing and Buffering.Shrirang K. Karandikar, Charles J. Alpert, Mehmet Can Yildiz, Paul Villarrubia, Stephen T. Quay, T. Mahmud
2007DACRQL: Global Placement via Relaxed Quadratic Spreading and Linearization.Natarajan Viswanathan, Gi-Joon Nam, Charles J. Alpert, Paul Villarrubia, Haoxing Ren, Chris C. N. Chu
2005DACDiffusion-based placement migration.Haoxing Ren, David Zhigang Pan, Charles J. Alpert, Paul Villarrubia
2004ICCADTrue crosstalk aware incremental placement with noise map.Haoxing Ren, David Zhigang Pan, Paul Villarrubia
2003ICCADOn Whitespace and Stability in Mixed-Size Placement and Physical Synthesis.Saurabh N. Adya, Igor L. Markov, Paul Villarrubia
2002ICCADFree space management for cut-based placement.Charles J. Alpert, Gi-Joon Nam, Paul Villarrubia
2001DACA Practical Methodology for Early Buffer and Wire Resource Allocation.Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Paul Villarrubia
2000DAC"Timing closure by design, " a high frequency microprocessor design methodology.Stephen D. Posluszny, Naoaki Aoki, David Boerstler, Paula K. Coulman, Sang H. Dhong, Brian K. Flachs, H. Peter Hofstee, Nobuo Kojima, Ohsang Kwon, Kyung T. Lee, David Meltzer, Kevin J. Nowka, J. Park, J. Peter, Joel Silberman, Osamu Takahashi, Paul Villarrubia
2000DATETransformational Placement and Synthesis.Wilm E. Donath, Prabhakar Kudva, Leon Stok, Paul Villarrubia, Lakshmi N. Reddy, Andrew Sullivan, Kanad Chakraborty
1997ICCDAn Integrated Placement and Synthesis Approach for Timing Closure of PowerPC Microprocessors.Shervin Hojat, Paul Villarrubia
1989ICCDIBM RISC chip design methodology.Paul Villarrubia, Gary Nusbaum, Robert Masleid, P. T. Patel