Phoebe Wong
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
1
Venues
1
Active years
2005–2005
Best venue rank
A*
Where they publish
Papers
1 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2005 | DAC | Device and architecture co-optimization for FPGA power reduction. | Lerong Cheng, Phoebe Wong, Fei Li, Yan Lin, Lei He |