Pierre-Yves Robert
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
1
Venues
1
Active years
2013–2013
Best venue rank
C
Where they publish
Papers
1 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2013 | IECON | Validation of eHS FPGA reconfigurable low-latency electric and power electronic circuit solver. | Jean Blanger, Amine Yamane, Andy Yen, Sbastien Cense, Pierre-Yves Robert |