| 2026 | ISCAS | Energy-Efficient All-Digital Computation-in-Memory Macro Design with CFeFET-based Booth Decoder. | Ting-Wei Yang, Wei Lu, Yuan-Yu Huang, Pin Su, Po-Tsang Huang |
| 2017 | ISCAS | Exploration and evaluation of low-dropout linear voltage regulator with FinFET, TFET and hybrid TFET-FinFET implementations. | Chia-Ning Chang, Yin-Nien Chen, Po-Tsang Huang, Pin Su, Ching-Te Chuang |
| 2016 | ISCAS | Investigation of BTI reliability for monolithic 3D 6T SRAM with ultra-thin-body GeOI MOSFETs. | Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang |
| 2016 | ISLPED | Benchmarking of Monolayer and Bilayer Two-Dimensional Transition Metal Dichalcogenide (TMD) Based Logic Circuits and 6T SRAM Cells. | Chang-Hung Yu, Pin Su, Ching-Te Chuang |
| 2015 | ISCAS | Evaluation of TFET and FinFET devices and 32-Bit CLA circuits considering work function variation and line-edge roughness. | Chien-Ju Chen, Yin-Nien Chen, Ming-Long Fan, Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang |
| 2015 | ISCAS | Impacts of NBTI and PBTI on ultra-thin-body GeOI 6T SRAM cells. | Vita Pi-Ho Hu, Ming-Long Fan, Pin Su, Ching-Te Chuang |
| 2014 | ISCAS | Investigation and optimization of monolithic 3D logic circuits and SRAM cells considering interlayer coupling. | Ming-Long Fan, Vita Pi-Ho Hu, Yin-Nien Chen, Pin Su, Ching-Te Chuang |
| 2014 | ISCAS | Evaluation of Read- and Write-Assist circuits for GeOI FinFET 6T SRAM cells. | Vita Pi-Ho Hu, Ming-Long Fan, Pin Su, Ching-Te Chuang |
| 2014 | ISLPED | Ultra-low voltage mixed TFET-MOSFET 8T SRAM cell. | Yin-Nien Chen, Ming-Long Fan, Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang |
| 2011 | ISLPED | Analysis of power-performance for ultra-thin-body GeOI logic circuits. | Vita Pi-Ho Hu, Ming-Long Fan, Pin Su, Ching-Te Chuang |
| 2009 | ISLPED | Design and analysis of ultra-thin-body SOI based subthreshold SRAM. | Vita Pi-Ho Hu, Yu-Sheng Wu, Ming-Long Fan, Pin Su, Ching-Te Chuang |