Po-Cheng Pan
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
6
Venues
3
Active years
2011–2019
Best venue rank
A*
Where they publish
Papers
6 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2019 | DAC | An Efficient Learning-based Approach for Performance Exploration on Analog and RF Circuit Synthesis. | Po-Cheng Pan, Chien-Chia Huang, Hung-Ming Chen |
| 2018 | DAC | Analog placement with current flow and symmetry constraints using PCP-SP. | Abhishek Patyal, Po-Cheng Pan, K. A. Asha, Hung-Ming Chen, Hao-Yu Chi, Chien-Nan Liu |
| 2013 | DATE | PAGE: parallel agile genetic exploration towards utmost performance for analog circuit design. | Po-Cheng Pan, Hung-Ming Chen, Chien-Chih Lin |
| 2013 | ICCAD | Efficient analog layout prototyping by layout reuse with routing preservation. | Ching-Yu Chin, Po-Cheng Pan, Hung-Ming Chen, Tung-Chieh Chen, Jou-Chun Lin |
| 2012 | ICCAD | Configurable analog routing methodology via technology and design constraint unification. | Po-Cheng Pan, Hung-Ming Chen, Yi-Kan Cheng, Jill Liu, Wei-Yi Hu |
| 2011 | ICCAD | Fast analog layout prototyping for nanometer design migration. | Yi-Peng Weng, Hung-Ming Chen, Tung-Chieh Chen, Po-Cheng Pan, Chien-Hung Chen, Wei-Zen Chen |