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Po-Chih Tseng

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

8

Venues

4

Active years

2002–2005

Best venue rank

C

Where they publish

Papers

8 indexed papers, newest first.

Year	Venue	Title	Authors
2005	ISCAS	Multiple-lifting scheme: memory-efficient VLSI implementation for line-based 2-D DWT.	Chih-Chi Cheng, Chao-Tsung Huang, Po-Chih Tseng, Chia-Ho Pan, Liang-Gee Chen
2004	ICASSP	Memory analysis and architecture for two-dimensional discrete wavelet transform.	Chao-Tsung Huang, Po-Chih Tseng, Liang-Gee Chen
2004	ISCAS	B-spline factorization-based architecture for inverse discrete wavelet transform.	Chao-Tsung Huang, Po-Chih Tseng, Liang-Gee Chen
2004	ISCAS	Low-power parallel tree architecture for full search block-matching motion estimation.	Siou-Shen Lin, Po-Chih Tseng, Liang-Gee Chen
2004	ISCAS	Reconfigurable discrete cosine transform processor for object-based video signal processing.	Po-Chih Tseng, Chao-Tsung Huang, Liang-Gee Chen
2003	ICIP	Hardware implementation of shape-adaptive discrete wavelet transform with the JPEG2000 defaulted (9, 7) filter bank.	Chao-Tsung Huang, Po-Chih Tseng, Liang-Gee Chen
2002	ISCAS	Efficient VLSI architectures of lifting-based discrete wavelet transform by systematic design method.	Chao-Tsung Huang, Po-Chih Tseng, Liang-Gee Chen
2002	VCIP	VLSI implementation of shape-adaptive discrete wavelet transform.	Po-Chih Tseng, Chao-Tsung Huang, Liang-Gee Chen