Po-Han Wang
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
7
Venues
5
Active years
2010–2021
Best venue rank
A*
Where they publish
Papers
7 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2021 | NSDI | SyncScatter: Enabling WiFi like synchronization and range for WiFi backscatter Communication. | Manideep Dunna, Miao Meng, Po-Han Wang, Chi Zhang, Patrick P. Mercier, Dinesh Bharadia |
| 2018 | DAC | Active forwarding: eliminate IOMMU address translation for accelerator-rich architectures. | Hsueh-Chun Fu, Po-Han Wang, Chia-Lin Yang |
| 2017 | ASPDAC | Enabling fast preemption via Dual-Kernel support on GPUs. | Li-Wei Shieh, Kun-Chih Chen, Hsueh-Chun Fu, Po-Han Wang, Chia-Lin Yang |
| 2017 | ISPASS | Analyzing OpenCL 2.0 workloads using a heterogeneous CPU-GPU simulator. | Li Wang, Ren-Wei Tsai, Shao-Chung Wang, Kun-Chih Chen, Po-Han Wang, Hsiang-Yun Cheng, Yi-Chung Lee, Sheng-Jie Shu, Chun-Chieh Yang, Min-Yih Hsu, Li-Chen Kan, Chao-Lin Lee, Tzu-Chieh Yu, Rih-Ding Peng, Chia-Lin Yang, Yuan-Shin Hwang, Jenq Kuen Lee, Shiao-Li Tsao, Ming Ouhyoung |
| 2016 | DAC | Latency sensitivity-based cache partitioning for heterogeneous multi-core architecture. | Po-Han Wang, Cheng-Hsuan Li, Chia-Lin Yang |
| 2012 | ISPASS | A cycle-level SIMT-GPU simulation framework. | Po-Han Wang, Chien-Wei Lo, Chia-Lin Yang, Yu-Jung Cheng |
| 2010 | DATE | PM-COSYN: PE and memory co-synthesis for MPSoCs. | Yi-Jung Chen, Chia-Lin Yang, Po-Han Wang |