| 2021 | IJCNN | A Spatial-Temporal Graph Attention Network for Multi-intersection Traffic Light Control. | Liu He, Qing'an Li, Libing Wu, Min Wang, Jianxin Li, Dan Wu |
| 2015 | DAC | Compiler directed automatic stack trimming for efficient non-volatile processors. | Qing'an Li, Mengying Zhao, Jingtong Hu, Yongpan Liu, Yanxiang He, Chun Jason Xue |
| 2015 | DATE | Software assisted non-volatile register reduction for energy harvesting based cyber-physical system. | Mengying Zhao, Qing'an Li, Mimi Xie, Yongpan Liu, Jingtong Hu, Chun Jason Xue |
| 2014 | DAC | Write Mode Aware Loop Tiling for High Performance Low Power Volatile PCM. | Keni Qiu, Qing'an Li, Chun Jason Xue |
| 2014 | DATE | A wear-leveling-aware dynamic stack for PCM memory in embedded systems. | Qing'an Li, Yanxiang He, Yong Chen, Chun Jason Xue, Nan Jiang, Chao Xu |
| 2014 | ISCAS | Register allocation for hybrid register architecture in nonvolatile processors. | Yiqun Wang, Hongyang Jia, Yongpan Liu, Qing'an Li, Chun Jason Xue, Huazhong Yang |
| 2013 | ASPDAC | Compiler-assisted refresh minimization for volatile STT-RAM cache. | Qing'an Li, Jianhua Li, Liang Shi, Chun Jason Xue, Yiran Chen, Yanxiang He |
| 2013 | CASES | Minimizing code size via page selection optimization on partitioned memory architectures. | Mengting Yuan, Chun Jason Xue, Yong Chen, Qing'an Li, Yingchao Zhao |
| 2013 | DATE | Cache coherence enabled adaptive refresh for volatile STT-RAM. | Jianhua Li, Liang Shi, Qing'an Li, Chun Jason Xue, Yiran Chen, Yinlong Xu |
| 2012 | ISLPED | MAC: migration-aware compilation for STT-RAM based hybrid cache in embedded systems. | Qing'an Li, Jianhua Li, Liang Shi, Chun Jason Xue, Yanxiang He |
| 2011 | TrustCom | Minimizing Schedule Length via Cooperative Register Allocation and Loop Scheduling for Embedded Systems. | Yazhi Huang, Qing'an Li, Chun Jason Xue |