| 2026 | ASPLOS | Compass: Navigating the Design Space of Taint Schemes for RTL Security Verification. | Yuheng Yang, Qinhan Tan, Thomas Bourgeat, Sharad Malik, Mengjia Yan |
| 2026 | DATE | SecIC3: Customizing IC3 for Hardware Security Verification. | Qinhan Tan, Akash Gaonkar, Yu-Wei Fan, Aarti Gupta, Sharad Malik |
| 2026 | SP | Interplay of Efficient Model Checking and Secure Processor Design: A Case Study on Secure Speculation. | Tingzhen Dong, Qinhan Tan, Kunpeng Wang, Thomas Bourgeat, Yuheng Yang, Sharad Malik, Yu-Wei Fan, Mengjia Yan |
| 2025 | ASPLOS | RTL Verification for Secure Speculation Using Contract Shadow Logic. | Qinhan Tan, Yuheng Yang, Thomas Bourgeat, Sharad Malik, Mengjia Yan |
| 2025 | ASPLOS | DejaVuzz: Disclosing Transient Execution Bugs with Dynamic Swappable Memory and Differential Information Flow Tracking Assisted Processor Fuzzing. | Jinyan Xu, Yangye Zhou, Xingzhi Zhang, Yinshuai Li, Qinhan Tan, Yinqian Zhang, Yajin Zhou, Rui Chang, Wenbo Shen |
| 2023 | CCS | Security Verification of Low-Trust Architectures. | Qinhan Tan, Yonathan Fisseha, Shibo Chen, Lauren Biernacki, Jean-Baptiste Jeannin, Sharad Malik, Todd M. Austin |
| 2022 | ICCAD | Usage-Based RTL Subsetting for Hardware Accelerators. | Qinhan Tan, Aarti Gupta, Sharad Malik |
| 2020 | ISCAS | Efficacy of Satisfiability-Based Attacks in the Presence of Circuit Reverse-Engineering Errors. | Qinhan Tan, Seetal Potluri, Aydin Aysu |
| 2020 | NDSS | PhantomCache: Obfuscating Cache Conflicts with Localized Randomization. | Qinhan Tan, Zhihua Zeng, Kai Bu, Kui Ren |