| 2008 | DSD | Exploiting Internal Operation Patterns during the High-Level Synthesis of Time-Constrained Circuits. | Pedro Garcia-Repetto, Mara C. Molina, Rafael Ruiz-Sautua, Guillermo Botella Juan |
| 2007 | DATE | Area optimization of multi-cycle operators in high-level synthesis. | Mara C. Molina, Rafael Ruiz-Sautua, Jose Manuel Mendias, Romn Hermida |
| 2006 | DATE | Pre-synthesis optimization of multiplications to improve circuit performance. | Rafael Ruiz-Sautua, Mara C. Molina, Jos M. Mendas, Romn Hermida |
| 2005 | ASPDAC | Arrival time aware scheduling to minimize clock cycle length. | Rafael Ruiz-Sautua, Mara C. Molina, Jos M. Mendas, Romn Hermida |
| 2005 | DATE | Behavioural Transformation to Improve Circuit Performance in High-Level Synthesis. | Rafael Ruiz-Sautua, Mara C. Molina, Jos M. Mendas, Romn Hermida |
| 2005 | ICCAD | Performance-driven read-after-write dependencies softening in high-level synthesis. | Rafael Ruiz-Sautua, Mara C. Molina, Jose Manuel Mendias, Romn Hermida |
| 2004 | DATE | Behavioural Bitwise Scheduling Based on Computational Effort Balancing. | Mara C. Molina, Rafael Ruiz-Sautua, Jos M. Mendas, Romn Hermida |