| 2025 | FDL | A Quantitative Guide to Navigate Speed/Accuracy Tradeoffs in System Level Design of RISC-V Processor Grids. | Lars Luchterhandt, Vivek Govindasamy, Yutong Wang, Christoph Scheytt, Wolfgang Mller, Rainer Dmer |
| 2024 | DATE | BusyMap, an Efficient Data Structure to Observe Interconnect Contention in SystemC TLM-2.0. | Emad Malekzadeh Arasteh, Vivek Govindasamy, Rainer Dmer |
| 2023 | FDL | Instruction-Level Modeling and Evaluation of a Cache-Less Grid of Processing Cells. | Vivek Govindasamy, Rainer Dmer |
| 2021 | FDL | Improving Parallelism in System Level Models by Assessing PDES Performance. | Emad Malekzadeh Arasteh, Rainer Dmer |
| 2020 | ASPDAC | Event Delivery using Prediction for Faster Parallel SystemC Simulation. | Zhongqi Cheng, Emad Malekzadeh Arasteh, Rainer Dmer |
| 2020 | DATE | Lazy Event Prediction using Defining Trees and Schedule Bypass for Out-of-Order PDES. | Daniel Mendoza, Zhongqi Cheng, Emad Malekzadeh Arasteh, Rainer Dmer |
| 2018 | DATE | Port call path sensitive conflict analysis for instance-aware parallel SystemC simulation. | Tim Schmidt, Zhongqi Cheng, Rainer Dmer |
| 2018 | FDL | SystemC Coding Guideline for Faster Out-of-order Parallel Discrete Event Simulation. | Zhongqi Cheng, Tim Schmidt, Rainer Dmer |
| 2017 | ASPDAC | Hybrid analysis of SystemC models for fast and accurate parallel simulation. | Tim Schmidt, Guantao Liu, Rainer Dmer |
| 2017 | DAC | Exploiting Thread and Data Level Parallelism for Ultimate Parallel SystemC Simulation. | Tim Schmidt, Guantao Liu, Rainer Dmer |
| 2016 | SCOPES | Automatic Generation of Thread Communication Graphs from SystemC Source Code. | Tim Schmidt, Guantao Liu, Rainer Dmer |
| 2015 | ASPDAC | Communication protocol analysis of transaction-level models using Satisfiability Modulo Theories. | Che-Wei Chang, Rainer Dmer |
| 2015 | ASPDAC | Optimizing thread-to-core mapping on manycore platforms with distributed Tag Directories. | Guantao Liu, Tim Schmidt, Rainer Dmer, Ajit Dingankar, Desmond Kirkpatrick |
| 2015 | DATE | May-happen-in-parallel analysis of ESL models using UPPAAL model checking. | Che-Wei Chang, Rainer Dmer |
| 2014 | DATE | May-happen-in-parallel analysis based on segment graphs for safe ESL models. | Weiwei Chen, Xu Han, Rainer Dmer |
| 2014 | FDL | Powermonitor: a versatile API for automated power-aware ESL design. | Yasaman Samei Syahkal, Rainer Dmer |
| 2014 | IPCCC | Automated estimation of power consumption for rapid system level design. | Yasaman Samei Syahkal, Rainer Dmer |
| 2013 | DATE | Optimized out-of-order parallel discrete event simulation using predictions. | Weiwei Chen, Rainer Dmer |
| 2013 | SCOPES | Designer-in-the-loop recoding of ESL models using static parallel access conflict analysis. | Xu Han, Weiwei Chen, Rainer Dmer |
| 2012 | ASPDAC | An optimizing compiler for out-of-order parallel ESL simulation exploiting instance isolation. | Weiwei Chen, Rainer Dmer |
| 2012 | ASPDAC | Parallel discrete event simulation of Transaction Level Models. | Rainer Dmer, Weiwei Chen, Xu Han |
| 2012 | DATE | Out-of-order parallel simulation for ESL design. | Weiwei Chen, Xu Han, Rainer Dmer |
| 2011 | ASPDAC | Multi-core parallel simulation of System-level Description Languages. | Rainer Dmer, Weiwei Chen, Xu Han, Andreas Gerstlauer |
| 2010 | ASPDAC | A fast heuristic scheduling algorithm for periodic ConcurrenC models. | Weiwei Chen, Rainer Dmer |
| 2010 | ASPDAC | Computer-aided recoding for multi-core systems. | Rainer Dmer |
| 2010 | ASPDAC | System-level development of embedded software. | Gunar Schirner, Andreas Gerstlauer, Rainer Dmer |
| 2010 | DATE | Panel Session - Who Is Closing the embedded software design gap? | Wolfgang Ecker, Pierre Bricaud, Rainer Dmer, Yossi Veller, Stefan Heinen, Jrgen Mssinger, Andreas von Schwerin |
| 2009 | ASPDAC | Introduction to hardware-dependent software design hardware-dependent software for multi- and many-core embedded systems. | Rainer Dmer, Andreas Gerstlauer, Wolfgang Mller |
| 2009 | DATE | Programming MPSoC platforms: Road works ahead! | Rainer Leupers, Andras Vajda, Marco Bekooij, Soonhoi Ha, Rainer Dmer, Achim Nohl |
| 2008 | ASPDAC | Automatic re-coding of reference code into structured and analyzable SoC models. | Pramod Chandraiah, Rainer Dmer |
| 2008 | ASPDAC | Automatic generation of hardware dependent software for MPSoCs from abstract system specifications. | Gunar Schirner, Andreas Gerstlauer, Rainer Dmer |
| 2008 | DATE | Introducing Preemptive Scheduling in Abstract RTOS Models using Result Oriented Modeling. | Gunar Schirner, Rainer Dmer |
| 2007 | ASPDAC | Creating Explicit Communication in SoC Models Using Interactive Re-Coding. | Pramod Chandraiah, Junyu Peng, Rainer Dmer |
| 2007 | ASPDAC | Abstract, Multifaceted Modeling of Embedded Processors for System Level Design. | Gunar Schirner, Andreas Gerstlauer, Rainer Dmer |
| 2007 | DAC | Designer-Controlled Generation of Parallel and Flexible Heterogeneous MPSoC Specification. | Pramod Chandraiah, Rainer Dmer |
| 2006 | DATE | Quantitative analysis of transaction level models for the AMBA bus. | Gunar Schirner, Rainer Dmer |
| 2006 | DSD | A Flexible, Syntax Independent Representation (SIR) for System Level Design Models. | Ines Viskic, Rainer Dmer |
| 2006 | ICCAD | Fast and accurate transaction level models using result oriented modeling. | Gunar Schirner, Rainer Dmer |
| 2005 | ASPDAC | System-level communication modeling for network-on-chip synthesis. | Andreas Gerstlauer, Dongwan Shin, Rainer Dmer, Daniel D. Gajski |
| 2004 | ASPDAC | Embedded software generation from system level design languages. | Haobo Yu, Rainer Dmer, Daniel Gajski |
| 2000 | ASPDAC | Reuse and protection of intellectual property in the SpecC system. | Rainer Dmer, Daniel Gajski |
| 1997 | ASPDAC | Built-in chaining: introducing complex components into architectural synthesis. | Peter Marwedel, Birger Landwehr, Rainer Dmer |
| 1996 | DATE | A Technique for Avoiding Isomorphic Netlists in Architectural Synthesis. | Peter Marwedel, Steven Bashford, Rainer Dmer, Birger Landwehr, Ingolf Markhof |