Rajnish Ghughal
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
6
Venues
4
Active years
1998–2014
Best venue rank
A*
Where they publish
Papers
6 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2014 | FM | Formally Verifying Graphics FPU - An Intel Experience. | Aarti Gupta, V. M. Achutha KiranKumar, Rajnish Ghughal |
| 2012 | FMCAD | Symbolic Trajectory Evaluation: The primary validation Vehicle for next generation Intel Processor Graphics FPU. | V. M. Achutha KiranKumar, Aarti Gupta, Rajnish Ghughal |
| 2009 | CAV | Replacing Testing with Formal Verification in Intel CoreTM i7 Processor Execution Engine Validation. | Roope Kaivola, Rajnish Ghughal, Naren Narasimhan, Amber Telfer, Jesse Whittemore, Sudhindra Pandav, Anna Slobodov, Christopher Taylor, Vladimir A. Frolov, Erik Reeber, Armaghan Naik |
| 2000 | FMCAD | Applications of Hierarchical Verification in Model Checking. | Robert Beers, Rajnish Ghughal, Mark D. Aagaard |
| 1998 | CAV | The 'Test Model-Checking' Approach to the Verification of Formal Memory Models of Multiprocessors. | Ratan Nalumasu, Rajnish Ghughal, Abdelillah Mokkedem, Ganesh Gopalakrishnan |
| 1998 | SPAA | Using "Test Model-Checking" to Verify the Runway-PA8000 Memory Model. | Rajnish Ghughal, Abdelillah Mokkedem, Ratan Nalumasu, Ganesh Gopalakrishnan |