| 2023 | CoDIT | Improving Integrated Circuit Security Using Mathematical Model Based on Clique Covering Reformulation. | Jonathan Fontaine, Mohamed Benazouz, Lilia Zaourar, Roselyne Chotin |
| 2022 | ISCAS | Using HLS for Designing a Parametric Optical Flow Hierarchical Algorithm in FPGAs. | Ilias Bournias, Roselyne Chotin, Lionel Lacassagne |
| 2022 | MODELSWARD | Model to Hardware: System-level Modeling for Wearable Devices. | Daniela Genius, Roselyne Chotin |
| 2021 | ISCAS | FPGA Acceleration of the Horn and Schunck Hierarchical Algorithm. | Ilias Bournias, Roselyne Chotin, Lionel Lacassagne |
| 2020 | FDL | Virtual Prototyping of Open Source Heterogeneous Systems with an Open Source Framework Featuring SystemC MDVP Extensions. | Franois Pcheux, Liliana Andrade, Marie-Minerve Lourat, Ilias Bournias, Roselyne Chotin, Daniela Genius |
| 2020 | MODELSWARD | High-level Partitioning and Design Space Exploration for Cyber Physical Systems. | Daniela Genius, Ilias Bournias, Ludovic Apvrille, Roselyne Chotin |
| 2020 | MODELSWARD | Model-Based Virtual Prototyping of CPS: Application to Bio-Medical Devices. | Daniela Genius, Ilias Bournias, Ludovic Apvrille, Roselyne Chotin |
| 2020 | WAIFI | A HDL Generator for Flexible and Efficient Finite-Field Multipliers on FPGAs. | Jol Cathbras, Roselyne Chotin |