Sayeeda Sultana
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
3
Venues
2
Active years
2011–2011
Best venue rank
C
Where they publish
Papers
3 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2011 | ICCD | Positive Davio-based synthesis algorithm for reversible logic. | Yu Pang, Shaoquan Wang, Zhilong He, Jinzhao Lin, Sayeeda Sultana, Katarzyna Radecka |
| 2011 | ICCD | A study on relating redundancy removal in classical circuits to reversible mapping. | Sayeeda Sultana, Katarzyna Radecka, Yu Pang |
| 2011 | ISCAS | A novel method of synthesizing reversible logic. | Yu Pang, Jinzhao Lin, Sayeeda Sultana, Katarzyna Radecka |