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Shian-Ru Lin

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

10

Venues

1

Active years

2017–2026

Best venue rank

C

Where they publish

Papers

10 indexed papers, newest first.

YearVenueTitleAuthors
2026ISCASA Dual-Hysteresis Synthetic Current Control in a Single-Inductor Multiple-Output Converter for Dynamic Voltage Scaling and 0.02mV/mA Cross Regulation.Meng-Zhen Liu, Chieh-Sheng Hung, Yu-Tse Shih, Xiao-Quan Wu, Ya-Ting Hsu, Ke-Horng Chen, Ying-Hsi Lin, Shian-Ru Lin, Tsung-Yen Tsai, Xi Zhu
2026ISCASA Dynamic Buffer Region for 0.104 to 9.6 Wide Voltage Conversion Range in An Extensive Current Optimization Buck-Boost Converter for USB PD 3.2.Yen-An Tsai, Yu-Teng Liang, Ya-Ting Hsu, Ke-Horng Chen, Xi Zhu, Ying-Hsi Lin, Shian-Ru Lin, Tsung-Yen Tsai
2025ISCASA 16.42 TOPS/mmTsung-Han Wu, Yu-Tse Shih, Hsin-Yung Fu, Chia Ling Ho, Wai-Chi Fang, Ke-Horng Chen, Kuo-Lin Zheng, Ying-Hsi Lin, Shian-Ru Lin, Tsung-Yen Tsai, Jui-Jen Wu, Meng-Fan Marvin Chang
2022ISCASA Dual-Mode Seamless Transition Low-Dropout Regulator with Improved Load Transient Response for RF Energy-Harvesting Application.Tzu-Yu Tzeng, Sheng Cheng Lee, Ke-Horng Chen, Ying-Hsi Lin, Shian-Ru Lin, Tsung-Yen Tsai
2022ISCASTriple Binary SAR Control in Distributive Digital Low Dropout Regulators for 3.6ns Fast Transient Response and 0.4mV Low Output Voltage Ripple.Bo-Kuan Wu, Tzu-Ying Wu, Sheng Cheng Lee, Ke-Horng Chen, Ying-Hsi Lin, Shian-Ru Lin, Tsung-Yen Tsai
2021ISCASA Series Stacked FinFET Structure for Digital Low Dropout Regulators with Minimum Energy Point Technique for 37.5% Energy Reduction in Cortex M0 Processor.Nan-Hsiung Tseng, Bo-Kuan Wu, Tzu-Ping Huang, Cheng-Yen Lee, Ke-Horng Chen, Ying-Hsi Lin, Shian-Ru Lin, Tsung-Yen Tsai
2020ISCASRGB Virtual Pixel MicroLED Display with a Supply Buffer for Reducing Ghosting by 50%-73% and Achieving 4 Times Screen Resolution and 95% High Efficiency.Kai-Cheng Chung, Zhi-Qiang Zhang, Cheng-Hsiang Liao, Yu-Yung Kao, Ke-Horng Chen, Ying-Hsi Lin, Shian-Ru Lin, Tsung-Yen Tsai
2020ISCASA 8-ns Settling Time Fully Integrated LDO with Dynamic Biasing and Bulk Modulation Techniques in 40nm CMOS.T. Nagateja, Neha Kumari, Ke-Horng Chen, Ying-Hsi Lin, Shian-Ru Lin, Tsung-Yen Tsai
2019ISCASAn Active Resonant Circuit with the Dynamic Resonant Period Control Technique for Fast Zero Voltage Switching in GaN-Based Active Clamp Flyback Converters.Jia-Jyun Lee, Jiang-Yue Wu, Mu-Wei Lee, Ke-Horng Chen, Ying-Hsi Lin, Shian-Ru Lin, Tsung-Yen Tsai
2017ISCASA digital reverse current self-calibration technique in 90% high efficiency rectified power supply for near field communication through magnetic field induction.Li-Chi Lin, Kuan-Yu Chen, Wen-Hau Yang, Ru-Yu Huang, Ke-Horng Chen, Ying-Hsi Lin, Shian-Ru Lin, Tsung-Yen Tsai