Shixin Chen
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
5
Venues
4
Active years
2024–2026
Best venue rank
A*
Where they publish
Papers
5 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2026 | DATE | IP-Matcher: An Efficient One-to-Many Matching Framework for Analog Circuit Design and Reusing. | Shixin Chen, Peng Xu, Yapeng Li, Tinghuan Chen, Bei Yu |
| 2025 | ASIACRYPT | Bootstrappable Fully Homomorphic Attribute-Based Encryption with Unbounded Circuit Depth. | Feixiang Zhao, Shixin Chen, Man Ho Au, Jian Weng, Huaxiong Wang, Jian Guo |
| 2025 | ASPDAC | The Survey of 2.5D Integrated Architecture: An EDA perspective. | Shixin Chen, Hengyuan Zhang, Zichao Ling, Jianwang Zhai, Bei Yu |
| 2024 | ASPDAC | SoC-Tuner: An Importance-guided Exploration Framework for DNN-targeting SoC Design. | Shixin Chen, Su Zheng, Chen Bai, Wenqian Zhao, Shuo Yin, Yang Bai, Bei Yu |
| 2024 | DAC | WinoGen: A Highly Configurable Winograd Convolution IP Generator for Efficient CNN Acceleration on FPGA. | Mingjun Li, Pengjia Li, Shuo Yin, Shixin Chen, Beichen Li, Chong Tong, Jianlei Yang, Tinghuan Chen, Bei Yu |