Siang-Yun Lee
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
10
Venues
5
Active years
2018–2025
Best venue rank
A*
Where they publish
Papers
10 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2025 | DAC | Logic Restructuring with Preserved Logic Blocks. | Siang-Yun Lee, Heinz Riener, Sascha Richter, Ankush Sood |
| 2024 | DAC | Late Breaking Results: Majority-Inverter Graph Minimization by Design Space Exploration. | Siang-Yun Lee, Alessandro Tempia Calvino, Heinz Riener, Giovanni De Micheli |
| 2024 | DATE | Technology-Aware Logic Synthesis for Superconducting Electronics. | Rassul Bairamkulov, Siang-Yun Lee, Alessandro Tempia Calvino, Dewmini Sudara Marakkalage, Mingfei Yu, Giovanni De Micheli |
| 2022 | ASPDAC | Boolean Rewriting Strikes Back: Reconvergence-Driven Windowing Meets Resynthesis. | Heinz Riener, Siang-Yun Lee, Alan Mishchenko, Giovanni De Micheli |
| 2022 | DAC | Beyond local optimality of buffer and splitter insertion for AQFP circuits. | Siang-Yun Lee, Heinz Riener, Giovanni De Micheli |
| 2022 | DATE | Majority-based Design Flow for AQFP Superconducting Family. | Giulia Meuli, Vinicius N. Possani, Rajinder Singh, Siang-Yun Lee, Alessandro Tempia Calvino, Dewmini Sudara Marakkalage, Patrick Vuillod, Luca G. Amar, Scott Chase, Jamil Kawa, Giovanni De Micheli |
| 2021 | ASPDAC | Algebraic and Boolean Optimization Methods for AQFP Superconducting Circuits. | Eleonora Testa, Siang-Yun Lee, Heinz Riener, Giovanni De Micheli |
| 2021 | DDECS | Logic Resynthesis of Majority-Based Circuits by Top-Down Decomposition. | Siang-Yun Lee, Heinz Riener, Giovanni De Micheli |
| 2019 | ICCAD | Searching Parallel Separating Hyperplanes for Effective Compression of Threshold Logic Networks. | Siang-Yun Lee, Nian-Ze Lee, Jie-Hong R. Jiang |
| 2018 | ICCAD | Canonicalization of threshold logic representation and its applications. | Siang-Yun Lee, Nian-Ze Lee, Jie-Hong R. Jiang |