| 2025 | DATE | Accurate and Extensible Symbolic Execution of Binary Code Based on Formal ISA Semantics. | Sren Tempel, Tobias Brandt, Christoph Lth, Christian Dietrich, Rolf Drechsler |
| 2023 | FDL | Minimally Invasive Generation of RISC-V Instruction Set Simulators from Formal ISA Models. | Sren Tempel, Tobias Brandt, Christoph Lth, Rolf Drechsler |
| 2022 | ASPDAC | Automated Detection of Spatial Memory Safety Violations for Constrained Devices. | Sren Tempel, Vladimir Herdt, Rolf Drechsler |
| 2022 | ATVA | SISL: Concolic Testing of Structured Binary Input Formats via Partial Specification. | Sren Tempel, Vladimir Herdt, Rolf Drechsler |
| 2022 | FDL | 3D Visualization of Symbolic Execution Traces. | Jan Zielasko, Sren Tempel, Vladimir Herdt, Rolf Drechsler |
| 2021 | ASPDAC | Mutation-based Compliance Testing for RISC-V. | Vladimir Herdt, Sren Tempel, Daniel Groe, Rolf Drechsler |
| 2021 | DAC | Towards Reliable Spatial Memory Safety for Embedded Software by Combining Checked C with Concolic Testing. | Sren Tempel, Vladimir Herdt, Rolf Drechsler |
| 2021 | DATE | An Effective Methodology for Integrating Concolic Testing with SystemC-based Virtual Prototypes. | Sren Tempel, Vladimir Herdt, Rolf Drechsler |
| 2021 | FDL | In-Vivo Stack Overflow Detection and Stack Size Estimation for Low-End Multithreaded Operating Systems using Virtual Prototypes. | Sren Tempel, Vladimir Herdt, Rolf Drechsler |
| 2020 | ICCD | Adaptive Simulation with Virtual Prototypes for RISC-V: Switching Between Fast and Accurate at Runtime. | Vladimir Herdt, Daniel Groe, Sren Tempel, Rolf Drechsler |