| 2011 | DAC | Power-gated MOS current mode logic (PG-MCML): a power aware DPA-resistant standard cell library. | Alessandro Cevrero, Francesco Regazzoni, Micheal Schwander, Stphane Badel, Paolo Ienne, Yusuf Leblebici |
| 2010 | CHES | ARMADILLO: A Multi-purpose Cryptographic Primitive Dedicated to Hardware. | Stphane Badel, Nilay Dagtekin, Jorge Nakahara Jr., Khaled Ouafi, Nicolas Reff, Pouyan Sepehrdad, Petr Susil, Serge Vaudenay |
| 2009 | CHES | A Design Flow and Evaluation Framework for DPA-Resistant Instruction Set Extensions. | Francesco Regazzoni, Alessandro Cevrero, Franois-Xavier Standaert, Stphane Badel, Theo Kluter, Philip Brisk, Yusuf Leblebici, Paolo Ienne |
| 2009 | ISCAS | Optimization of Wire Grid Size for Differential Routing and Impact on the Power-delay-area Tradeoff. | Massimo Alioto, Stphane Badel, Yusuf Leblebici |
| 2008 | DATE | A Generic Standard Cell Design Methodology for Differential Circuit Styles. | Stphane Badel, Erdem Guleyupoglu, Ozgur Inac, Anna Pena Martinez, Paolo Vietti, Frank K. Grkaynak, Yusuf Leblebici |
| 2007 | ISCAS | Breaking the Power-Delay Tradeoff: Design of Low-Power High-Speed MOS Current-Mode Logic Circuits Operating with Reduced Supply Voltage. | Stphane Badel, Yusuf Leblebici |
| 2006 | ISCAS | Via-programmable expanded universal logic gate in MCML for structured ASIC applications: circuit design. | Elizabeth J. Brauer, Ilhan Hatirnaz, Stphane Badel, Yusuf Leblebici |
| 2004 | ISCAS | Mixed analog-digital image processing circuit based on Hamming artificial neural network architecture. | Stphane Badel, Alexandre Schmid, Yusuf Leblebici |
| 2003 | ESANN | VLSI Realization of a Two-Dimensional Hamming Distance Comparator ANN for Image Processing Applications. | Stphane Badel, Alexandre Schmid, Yusuf Leblebici |
| 2003 | IJCNN | A VLSI Hamming artificial neural network with k-winner-take-all and k-loser-take-all capability. | Stphane Badel, Alexandre Schmid, Yusuf Leblebici |