Susumu Matsumae
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
8
Venues
4
Active years
2000–2013
Best venue rank
National
Where they publish
Papers
8 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2013 | HiPC | The super warp architecture with random address shift. | Koji Nakano, Susumu Matsumae |
| 2010 | ICA3PP | Efficient Partitioning of Static Buses for Processor Arrays of Small Size. | Susumu Matsumae |
| 2008 | PDPTA | Improving Hierarchical Power Saving Technique with Location Information for Sensor Networks. | Susumu Matsumae, Naoto Miyazaki |
| 2007 | PDPTA | Impact of Reconfigurability on Meshes with Row/Column Buses. | Susumu Matsumae |
| 2006 | PDPTA | Impact of Layered Buses on Scaling-Simulation of Reconfigurable Meshes. | Susumu Matsumae |
| 2006 | PDPTA | Scheduling Independent Tasks on Heterogeneous Parallel Computing Environments under the Unidirectional One-Port Model. | Fukuhito Ooshita, Susumu Matsumae, Toshimitsu Masuzawa |
| 2005 | PDPTA | Scaling-Simulation of Linear Reconfigurable Meshes by Horizontal-Vertical Reconfigurable Meshes. | Susumu Matsumae |
| 2000 | SPAA | An efficient self-simulation algorithm for reconfigurable meshes. | Susumu Matsumae, Nobuki Tokura |