| 2025 | ISCAS | A Pipelined-SAR ADC with a Compensation-Free Two-Stage Amplifier. | Chun-Tse Su, Chao-Yen Hsu, Shih-Jie Huang, Tai-Cheng Lee |
| 2022 | ISCAS | A Type-3 FMCW Radar Synthesizer with Wide Frequency Modulation Bandwidth. | Cheng-Tang Chen, Yu-Hong Yang, Tai-Cheng Lee |
| 2020 | ICCAD | /TPlace: Machine Learning-Based Delay-Aware Transistor Placement for Standard Cell Synthesis. | Tai-Cheng Lee, Cheng-Yen Yang, Yih-Lang Li |
| 2020 | ISCAS | A 5 GHz Outer-Loop Phase Noise Filter with Delay-Sampling Technique. | Kun-Ruei Li, Wei-Sung Chang, Tai-Cheng Lee |
| 2014 | ISCAS | A 20-MHz BW 75-dB SFDR shifted-averaging VCO-based ΔΣ modulator. | Yu-Hsuan Kang, Chin-Yu Lin, Tai-Cheng Lee |
| 2005 | ISCAS | An optimization technique for RF buffers with active inductors. | Tai-Cheng Lee, Yen-Chuan Huang |
| 2005 | ISCAS | A linear-approximation technique for digitally-calibrated pipelined A/D converters. | Ding-Lan Shen, Tai-Cheng Lee |
| 2004 | ISCAS | A 10 Gbase-LX4 receiver front end transimpedance amplifier and limiting amplifier. | Hung-Chieh Tsai, Jyh-Yih Yeh, Wei-Hsuan Tu, Tai-Cheng Lee, Chorng-Kuang Wang |
| 2002 | ISCAS | CMOS 2.4-GHz receiver front end with area-efficient inductors and digitally calibrated 90° delay network. | Chih-Chun Tang, Chia-Hsin Wu, Kun-Hsien Li, Tai-Cheng Lee, Shen-Iuan Liu |