Takashi Hasegawa
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
3
Venues
3
Active years
2005–2015
Best venue rank
A*
Where they publish
Papers
3 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2015 | DAC | Physically aware high level synthesis design flow. | Masato Tatsuoka, Ryosuke Watanabe, Tatsushi Otsuka, Takashi Hasegawa, Qiang Zhu, Ryosuke Okamura, Xingri Li, Tsuyoshi Takabatake |
| 2013 | SPLC | Case study of applying SPLE to development of network switch products. | Tadahisa Kato, Masumi Kawakami, Tomoyuki Myojin, Hideto Ogawa, Koji Hirono, Takashi Hasegawa |
| 2005 | DATE | Integrating UML into SoC Design Process. | Qiang Zhu, Ryosuke Oishi, Takashi Hasegawa, Tsuneo Nakata |