| 2022 | SPAA | HybriDS: Cache-Conscious Concurrent Data Structures for Near-Memory Processing Architectures. | Jiwon Choe, Andrew Crotty, Tali Moreshet, Maurice Herlihy, R. Iris Bahar |
| 2019 | DATE | IgnoreTM: Opportunistically Ignoring Timing Violations for Energy Savings using HTM. | Dimitra Papagiannopoulou, Sungseob Whang, Tali Moreshet, R. Iris Bahar |
| 2019 | SPAA | Concurrent Data Structures with Near-Data-Processing: an Architecture-Aware Implementation. | Jiwon Choe, Amy Huang, Tali Moreshet, Maurice Herlihy, R. Iris Bahar |
| 2016 | CASES | Thrifty-malloc: A HW/SW codesign for the dynamic management of hardware transactional memory in embedded multicore systems. | Thomas Carle, Dimitra Papagiannopoulou, Tali Moreshet, Andrea Marongiu, Maurice Herlihy, R. Iris Bahar |
| 2013 | ISCA | Transparent and energy-efficient speculation on NUMA architectures for embedded MPSoCs. | Dimitra Papagiannopoulou, R. Iris Bahar, Tali Moreshet, Maurice Herlihy, Andrea Marongiu, Luca Benini |
| 2011 | ICPADS | Power-Performance Comparison of Single-Task Driven Many-Cores. | Fuat Keceli, Tali Moreshet, Uzi Vishkin |
| 2010 | EuroPar | Thermal Management of a Many-Core Processor under Fine-Grained Parallelism. | Fuat Keceli, Tali Moreshet, Uzi Vishkin |
| 2006 | SPAA | Energy implications of multiprocessor synchronization. | Tali Moreshet, R. Iris Bahar, Maurice Herlihy |
| 2005 | ISLPED | Energy reduction in multiprocessor systems using transactional memory. | Tali Moreshet, R. Iris Bahar, Maurice Herlihy |
| 2003 | DAC | Power-aware issue queue design for speculative instructions. | Tali Moreshet, R. Iris Bahar |