Te-Jung Lo
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
1
Venues
1
Active years
2005–2005
Best venue rank
C
Where they publish
Papers
1 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2005 | ISCAS | VLSI architecture of low memory and high speed 2D lifting-based discrete wavelet transform for JPEG2000 applications. | Jen-Shiun Chiang, Chih-Hsien Hsia, Hsin-Jung Chen, Te-Jung Lo |