Todor Kostadinov
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
1
Venues
1
Active years
2015–2015
Best venue rank
C
Where they publish
Papers
1 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2015 | FQAS | Modeling Logic Gates and Circuits with Generalized Nets. | Lenko Erbakanov, Todor Kostadinov, Todor Petkov, Sotir Sotirov, Veselina Bureva |