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Tomasz Borejko

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

9

Venues

1

Active years

2008–2016

Best venue rank

C

Where they publish

Papers

9 indexed papers, newest first.

YearVenueTitleAuthors
2016DDECSBioSoC: Highly integrated System-on-Chip for health monitoring.Krzysztof Siwiec, Krzysztof Marcinek, Piotr Boguszewicz, Tomasz Borejko, Aleh Halauko, Adam Jarosz, Jakub Kopanski, Ewa Kurjata-Pfitzner, Pawel Narczyk, Maciej Plasota, Andrzej Wielgus, Witold A. Pleskacz
2012DDECSLC-VCO design automation tool for nanometer CMOS technology.Krzysztof Siwiec, Tomasz Borejko, Witold A. Pleskacz
2011DDECSA resistorless current reference source for 65 nm CMOS technology with low sensitivity to process, supply voltage and temperature variations.Michal Lukaszewicz, Tomasz Borejko, Witold A. Pleskacz
2011DDECSPVT tolerant LC-VCO in 90 nm CMOS technology for GPS/Galileo applications.Krzysztof Siwiec, Tomasz Borejko, Witold A. Pleskacz
2011DDECSCAD tool for PLL Design.Krzysztof Siwiec, Tomasz Borejko, Witold A. Pleskacz
2010DDECSA comparison of low voltage LNA architectures designed for multistandard GNSS in two 90 nm CMOS technologies.Jacek Gradzki, Tomasz Borejko, Witold A. Pleskacz
2009DDECSLow voltage LNA implementations in 90 nm CMOS technology for multistandard GNSS.Jacek Gradzki, Tomasz Borejko, Witold A. Pleskacz
2008DDECSBuilt-In Current Monitor for IDDQ Testing in CMOS 90 nm Technology.Marcin J. Beresinski, Tomasz Borejko, Witold A. Pleskacz, Viera Stopjakov
2008DDECSA Resistorless Voltage Reference Source for 90 nm CMOS Technology with Low Sensitivity to Process and Temperature Variations.Tomasz Borejko, Witold A. Pleskacz